A semiconductor typically contains a plurality of pockets of semiconductor material in which one or more circuit elements are formed. Conventionally, these semiconductor pockets are isolated by the LOCOS (Local Oxidation of Silicon) technique. However, the LOCOS technique has some disadvantages, especially in the fabrication of deep sub-micron very-high-density devices such as high density memory cells, because it can result in an undesirable isolation encroachment into the active device area, commonly known as "bird's beak". The LOCOS method also produces a non-planar surface when silicon oxide is grown on the surface of silicon, the thickness of the oxide which grows is typically twice the thickness of the silicon prior to oxidation.
Shallow trench isolation (STI) technique has been developed which offers several significant improvements over some aspects of the LOCOS process, especially in the fabrications of high density CMOS (complementary metal oxide semiconductor) circuits. In general, the STI process includes the steps of first etching a shallow trench (typically 0.5 .mu.m or less), then growing a thin oxide immediately after etch. Then the trench is filled with a dielectric by deposition of oxide, which also forms a top oxide layer above the substrate. The dielectric can be "densified," either by oxidizing the dielectric or using a high-temperature anneal in an inert ambient. Finally, the top oxide layer is planarized, typically by a chemical-mechanical polishing (CMP) process, using the top oxide layer as a sacrificial layer. Prior to the etching process, a silicon nitride layer (SiN.sub.x) is typically formed with the assistance of a photoresist. Due to its lower removal rate relative to the top oxide layer, the nitride layer serves as a CMP stop; it also serves as a hard mask during the etching process to form the trenches in the substrate. To protect the active regions from nitridation and achieve better process control, a thin pad oxide is typically thermally grown or deposited on the substrate surface prior to the deposition of the silicon nitride layer, and an oxide liner with good film quality can also be deposited on the surface of the trenches.
With the dimension of the trenches becoming smaller and the density of the semiconductor devices getting higher, several inadequacies are observed with the conventional shallow trench isolation process. Most notably, the oxide-filled trenches are often found to be subject to the so-called dishing effect during the CMP process. There are also problems associated with nitride residues that are found on the dished trench surface as well as on the top of active regions of the substrate, or oxide that remains on the nitride stoppers.
U.S. Pat. No. 5,741,740 discloses a method for filling a trench within a silicon substrate by first forming a trench in a silicon substrate, followed by thermally oxidizing the silicon substrate to form within the trench a thermal silicon oxide trench liner layer. A conformal silicon oxide intermediate layer is then formed upon the thermal silicon oxide trench liner through a plasma enhanced chemical vapor deposition (PECVD) employing a silane silicon source material. Finally, a gap filling silicon oxide trench fill layer is formed upon the conformal silicon oxide intermediate layer through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method employing an ozone oxidant and a tetra-ethyl-ortho-silicate (TEOS).
U.S. Pat. No. 5,643,822 discloses a method for improving the sub-threshold leakage of a trench-isolated FET device which involves the steps of first forming a vertical slot within a stack structure disposed on an oxide-covered silicon substrate, then forming spacers on the sidewalls of the slot. A trench is then etched in the substrate. A horizontal ledge on the exposed surfaces of the oxide-covered substrate adjacent the trench is uncovered after the removal of the spacers. The ledge is then perpendicularly implanted with a dopant to suppress edge conduction in the device.
U.S. Pat. No. 5,332,467 discloses a method of planarizing a wafer surface by using a polish step with chemical/mechanical polishing which involves first forming a first layer over a rugged surface of a semiconductor wafer with broad indentations. A hard film layer is formed over the first layer, whereby the first layer and the hard film layer are patterned to form polishing stop islands in the broad indentations. A second layer is then formed over the rugged surface and the polishing stop islands to create a top surface for polishing, the hard film layer being harder than both the top surface and the rugged surface. The top surface is polished in a vertical direction to remove portions of the top surface, until the top surface is co-planar with the top of the polishing stop islands, and finally the remainder of the hard film layer is removed to complete the planar surface.
U.S. Pat. No. 5,643,823 discloses the use of a thin crystalline layer of silicon nitride (Si.sub.3 N.sub.4) in shallow trench isolation structures as an O.sub.2 barrier film. It is reported that the crystalline Si.sub.3 N.sub.4 lowers the density of electron traps as compared to the as-deposited amorphous Si.sub.3 N.sub.4. The process of forming the crystalline Si.sub.3 N.sub.4 film in a shallow trench isolation (STI) structure comprises the steps of (1) depositing by low-pressure chemical-vapor deposition (LPCVD) a Si.sub.3 N.sub.4 film 5 to 10 nm thick within the STI structure at a temperature between 720 and 780.degree. C., and (2) immediately after the deposition of the Si.sub.3 N.sub.4 film, conducting a rapid-terminal anneal between 1,050 and 1,150.degree. C. for 60 seconds to convert the Si.sub.3 N.sub.4 film from an amorphous state to a crystalline state.
All the above mentioned inventions provide certain useful improvement in the formation of shallow trench isolation structures. However, none of them addressed the issue of how to eliminate or at least minimize the dishing problem during the CMP step in a relatively simple and cost-effective manner. In light of the growing importance of the STI structures and the planarization thereof, it is important to devote research and development effort for the improvement of the STI process.